VOL. XCIV, NO. 247
★ WIDE MOAT STOCKS & COMPETITIVE ADVANTAGES ★
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Taiwan Semiconductor Manufacturing Company Limited
2330 · Taiwan Stock Exchange
Weighted average of segment moat scores, combining moat strength, durability, confidence, market structure, pricing power, and market share.
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Overview
Taiwan Semiconductor Manufacturing Company Limited is the dominant pure-play foundry for global chip designers and system companies. The company reports one foundry operating segment; 1Q26 platform revenue was led by HPC at 61% and smartphones at 26%, while FY25 net revenue was NT$3.81tn. TrendForce put TSMC at 69.9% of the 2025 global foundry market and 70.4% in 4Q25. Its moat comes from capex scale, process-yield learning, dense design ecosystem, customer design-in qualification, and scarce advanced-node/CoWoS capacity. Main counter-pressures are customer concentration, semiconductor cyclicality, Taiwan geopolitical risk, export controls, subsidized rivals, and possible second-sourcing or open chiplet standards.
Primary segment
Semiconductor foundry services
Market structure
Quasi-Monopoly
Market share
69.9%-70.4% (reported)
HHI: 5,010
Coverage
1 segments · 6 tags
Updated 2026-04-24
Segments
Semiconductor foundry services
Global outsourced semiconductor foundry services
Revenue
100%
Structure
Quasi-Monopoly
Pricing
strong
Share
69.9%-70.4% (reported)
Peers
Moat Claims
Semiconductor foundry services
Global outsourced semiconductor foundry services
TSMC reports only one operating segment, the foundry segment. 1Q26 platform revenue was HPC 61%, smartphone 26%, IoT 6%, automotive 4%, digital consumer electronics 1% and others 2%. FY25 platform revenue was HPC 58%, smartphone 29%, IoT 5%, automotive 5%, digital consumer electronics 1% and others 2%.
Capex Knowhow Scale
Supply
Capex Knowhow Scale
Strength
Durability
Confidence
Evidence
TSMC combines massive capital deployment, owned fabs, engineering know-how and advanced-node scale that are hard for smaller foundries to replicate economically.
Erosion risks
- Semiconductor downcycles can turn fixed-cost scale into negative operating leverage.
- Government subsidies can help Samsung, Intel, Rapidus and regional foundries build uneconomic capacity.
- Geopolitical risk around Taiwan could impair customer willingness to concentrate supply.
Leading indicators
- Advanced-node wafer capacity additions
- Capacity utilization by node
- Capex intensity versus Samsung and Intel Foundry
Counterarguments
- Scale does not immunize TSMC from cyclical overcapacity.
- Sovereign industrial policy can fund competitors even when private returns are unattractive.
Learning Curve Yield
Supply
Learning Curve Yield
Strength
Durability
Confidence
Evidence
A long history of high-volume process ramps compounds yield, defect-density, cycle-time and manufacturing-control know-how, especially at 7nm-and-below nodes.
Erosion risks
- A major process inflection could reset accumulated yield advantages.
- Samsung or Intel Foundry could close the gap at a future node.
- Trade-secret leakage or talent loss could weaken process know-how advantages.
Leading indicators
- 2nm and 16-angstrom ramp milestones
- Advanced-node revenue share
- Yield and cycle-time customer commentary
Counterarguments
- Customers may push for second sources to avoid dependence on one leading-edge foundry.
- Technology leadership can narrow if rivals solve yield issues at a new transistor architecture.
Design In Qualification
Demand
Design In Qualification
Strength
Durability
Confidence
Evidence
Customer chips are designed around TSMC PDKs, IP libraries, mask sets, process rules and qualification flows, making late switching costly and risky.
Erosion risks
- Open chiplet standards and multi-foundry design flows could reduce process lock-in.
- Large system customers can fund porting work when second sourcing becomes strategically important.
- Export controls can force redesigns away from TSMC processes for restricted customers.
Leading indicators
- Tape-outs on N2, A16 and A14-class nodes
- PDK and IP readiness milestones
- CyberShuttle participation
Counterarguments
- Well-funded customers can port designs if supply assurance outweighs time-to-market risk.
- EDA and IP vendors also support competing foundries.
Ecosystem Complements
Network
Ecosystem Complements
Strength
Durability
Confidence
Evidence
OIP, EDA partners, IP libraries, 3DFabric reference flows, broad process coverage and a large customer base create complements that make TSMC the default advanced foundry platform.
Erosion risks
- EDA and IP vendors can make more flows multi-foundry.
- Open standards can reduce proprietary ecosystem dependence.
- Customer concentration may let the largest customers bypass parts of the ecosystem.
Leading indicators
- Number of OIP partners and certified IP blocks
- Process technologies deployed
- Products manufactured and customers served
Counterarguments
- Complementors are not exclusive to TSMC.
- A broader ecosystem can still be replicated for mature nodes or subsidized national foundry programs.
Capacity Moat
Supply
Capacity Moat
Strength
Durability
Confidence
Evidence
At leading-edge logic and advanced packaging, scarce qualified capacity can create allocation leverage and deepen customer dependence, but capacity advantages are cyclical.
Erosion risks
- Customer prepayments and capacity commitments can unwind in a downcycle.
- Rivals can add mature-node and selected advanced-node capacity with subsidies.
- If AI demand normalizes, CoWoS and leading-edge scarcity could ease.
Leading indicators
- Advance temporary receipts
- CoWoS capacity and lead times
- Utilization at 3nm, 2nm and advanced packaging lines
Counterarguments
- Capacity is a moat only when demand exceeds qualified supply.
- Overbuilding can turn capacity into a margin headwind.
Evidence
US$52 billion and US$56 billion
Shows planned 2026 capital expenditures at a scale few foundry competitors can match.
annual capacity (in 12-inch equivalent wafers) exceeded 17 million wafers
Supports scale in installed manufacturing capacity.
faster yield improvement and shorter cycle time
TSMC identifies yield improvement and cycle time as core competitive dimensions.
2-nanometer technology entered volume production in 2025
Supports continued leading-edge ramp execution.
accounted for 74% of total wafer revenue
Shows advanced-node processes are already high-volume, reinforcing learning effects.
Showing 5 of 16 sources.
Risks & Indicators
Erosion risks
- Semiconductor downcycles can turn fixed-cost scale into negative operating leverage.
- Government subsidies can help Samsung, Intel, Rapidus and regional foundries build uneconomic capacity.
- Geopolitical risk around Taiwan could impair customer willingness to concentrate supply.
- A major process inflection could reset accumulated yield advantages.
- Samsung or Intel Foundry could close the gap at a future node.
- Trade-secret leakage or talent loss could weaken process know-how advantages.
Leading indicators
- Advanced-node wafer capacity additions
- Capacity utilization by node
- Capex intensity versus Samsung and Intel Foundry
- Equipment lead times and fab ramp schedules
- 2nm and 16-angstrom ramp milestones
- Advanced-node revenue share
Curation & Accuracy
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